Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting

Abstract

The full-wave rectifier is the most straightforward way of extracting energy from a piezoelectric source. Unfortunately, the inherent capacitance of the piezo source significantly limits the efficiency of extraction. The bias-flip rectifier, which aims to mitigate this problem, not only needs a large inductor for efficient operation, but also needs precise tuning. We present the multi-stage bias-flip rectifier, which is a technique that achieves a high voltage-flip efficiency using a smaller inductor and relaxes timing-accuracy requirements. The rectifier, implemented in a 130 nm CMOS process, dissipates about 2 μ W and achieves a voltage-flip efficiency of 90% while using an inductor of only 47 μH.