Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting

Abstract

The full-wave rectifier is the most straightforward way of extracting energy from a piezoelectric source. Unfortunately, the inherent capacitance of the piezoelement significantly limits the efficiency of extraction. The bias-flip rectifier, which aims to mitigate this problem, not only needs a large inductor for efficient operation, but also needs the generation of pulses with a precisely defined ontime. A large inductor increases the overall volume of the system. We present the multi-stage bias-flip rectifier, which is a technique that achieves a high voltage-flip efficiency using a much smaller inductor, and relaxes timing-accuracy requirements. The rectifier, implemented in a 130-nm CMOS process, dissipates about 2 μW and achieves a voltage-flip efficiency of 89.5% while using only a 47 μH inductor.