Gatestacks for scalable high-performance FinFETsG. Vellianitis, Liangzhen Lai, S. Mertens et al.|Unknown|2007Cited by 32
Strain enhanced low-V<inf>T</inf> CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delayStefan Kubicek, Thomas Hoffmann, T. Schram et al.|Unknown|2008Cited by 9
Novel process to pattern selectively dual dielectric capping layers using soft-mask onlyT. Schram, S. Biesemans, Stefan Kubicek et al.|Unknown|2008Cited by 9