A twisted-bundle layout structure for minimizing inductive coupling noiseIn this paper, we propose a novel misted-bundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and re-order the routing of nets in each of these routing regions. The purpose is to create complementary and opposite current loops in the twisted-bundle layout structure, such that the magnetic fluxes arising from any signal net within a misted group cancel each other in the current loop of a net of interest. The effectiveness of the twisted-bundle structure in minimizing coupling inductance has been verified by the application of FastHenry extraction on a 16-bit bus structure. We achieve about two orders of magnitude reduction in inductive coupling. SPICE simulations also show that the 16-bit twisted-bundle bus structure is able to maintain high signal integrity at high frequency of operation. 1.
Stochastic wire-length and delay distributions of 3-dimensional circuits3-D technology promises higher integration density and lower in-terconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. In this paper, we in-vestigate the interconnect distributions of 3-D circuits. We divide the 3-D interconnects into horizontal wires and vertical wires and derive their wire-length distributions, respectively. Based on the stochastic wire-length distributions, we calculate 3-D circuit inter-connect delay distribution. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the num-ber of repeaters needed, and dramatically improve the performance. With 3-D structures, a circuit can work at a much higher clock rate (double, even triple) than with 2-D. However, we also show that the impacts of vertical wires on chip area and interconnect delay may limit the number of device layers that we can integrate. 1.
Selectively clocked skewed logic (SCSL)Article Share on Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications Authors: Naran Sirisantana School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Aiqun Cao School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Shawn Davidson School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Cheng Kok Koh School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001Pages 267–270https://doi.org/10.1145/383082.383160Published:06 August 2001Publication History 2citation164DownloadsMetricsTotal Citations2Total Downloads164Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access