Shiyou Zhao

We investigate the problem of decoupling capacitance (decap) allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given and consider the decap placement as a postfloorplan step. Second, we consider the decap placement as an integral part of a floorplanning methodology (noise-aware floorplanning). In both cases, the objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. Experimental results on MCNC benchmark circuits show that, for postfloorplan decap placement, the white space allocated for decap is about 6%-9% of the chip area for the 0.25-/spl mu/m technology. The power-supply noise is kept below the specified limit. Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduced by as much as 21% by using noise-aware floorplanning methodology. The total area is also reduced due to the reduced total decap budget gained from reduced power supply noise.

We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. Decoupling capacitance budgets for the circuit modules are calculated based on the power supply noise estimates. A linear programming technique is used to maximize the allocation of the existing white space in the floorplan for the placement of decoupling capacitors. An incremental heuristic is proposed to insert more white space into the existing floorplan to meet the remaining demand required for decoupling capacitance fabrication. Experimental results on six MCNC benchmark circuits show that the white space allocated for decoupling capacitance is about 6%-12% of the chip area for the 0.25μμ technology, and the power supply noise can be kept below 10%Vdd.

To achieve high performance and high integration density, the transistor dimensions are aggressively scaled down while lower power dissipation is achieved by scaling down the supply voltage. However, power distribution has become a challenging issue due to the severe switching noise on the power distribution network. Estimation of the worst case switching noise is essential to ensure the proper functionality of the VLSI circuits. In this paper, we propose a probabilistic approach to determine the lower bound of the worst case switching noise on power supply lines. The proposed algorithm traces the worst case input patterns which will induce the steepest maximum switching current spike and therefore the maximum switching noise. The worst case input patterns are used in the HSPICE simulation to extract the exact switching current waveforms. The estimated maximum switching current spike matches well with the peak current obtained from the HSPICE simulation. The worst case switching noise due to the lumped inductance (including the packaging inductance) and the lumped resistance on the power supply grid is also extracted from the HSPICE simulation. The magnitude of the worst case switching noise for the benchmark circuits implemented with 0.25 /spl mu/m technology can be as high as 35% of the Vdd. The switching noise can be suppressed effectively with properly placed decoupling capacitors.

In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (P/G) networks of tree topologies. We model the P/G network as a linear time invariant (LTI) pseudo-distributed RLC network and the gates (or cells) as time-varying current sources. Voltage fluctuation caused by the switching events is calculated based on the effective impedances seen by the corresponding current sources and the spatial correlation between the nodes of the power network. Superposition is applied to the LTI system to obtain the overall noise spectrum at any node of the power supply network. Inverse Fast Fourier Transformation (IFFT) is then performed on the frequency domain noise spectrum to obtain the time domain noise waveform. The proposed algorithm has a complexity of O#n 2 #. Experimental results show that our approach can produce accurate noise waveforms. 1.

Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modules based on their spatial correlations in the floorplan. In this paper, power supply noise is, for the first time, incorporated into the cost function to determine the optimal floorplan in terms of area, wire length, and power supply noise. Compared to the conventional floorplanning which only considers area and wire length, power supply noise aware floorplanning can generate better floorplan both in terms of area and peak noise. The decoupling capacitance required by each module is also calculated and placed in the vicinity of the target module during the floorplanning process. Experimental results on MCNC benchmark circuits show that the peak power supply noise can be reduced as much as 40 % and both the total area and wire length are improved due to the reduced total decoupling capacitance budget gained from reduced power supply noise. 1.