Selectively clocked skewed logic (SCSL)

Abstract

Article Share on Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications Authors: Naran Sirisantana School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Aiqun Cao School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Shawn Davidson School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Cheng Kok Koh School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001Pages 267–270https://doi.org/10.1145/383082.383160Published:06 August 2001Publication History 2citation164DownloadsMetricsTotal Citations2Total Downloads164Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access