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Alberto Sangiovanni‐Vincentelli

University of California, Berkeley

ORCID: 0000-0003-1298-8389

1.4k papers and 50.8k citations.

PubIndex Score98Top 2%How it's scored

🌟#1 Current Senior Leader in Formal Methods in Verification 🌟#2 Current Senior Leader in Embedded Systems Design Techniques 🌟#2 Current Senior Leader in VLSI and Analog Circuit Testing 🌟#3 Current Senior Leader in VLSI and FPGA Design Techniques 🌟#5 Current Senior Leader in Real-Time Systems Scheduling

1.4kPublications

50.8kTotal Citations

#1in Formal Methods in Verification

First publication: 1976First senior author: 1976

Top publicationsby citations

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

Yuan Lin, Alberto Sangiovanni‐Vincentelli|IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|2008

Cited by 43

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