A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation ApplicationsZhuoyu Dai, Ming Liu, Yifan He et al.|Unknown|2024Cited by 13
A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metricsShengzhe Yan, Ming Liu, Zi Wang et al.|Science China Information Sciences|2025Cited by 6
An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNetYongpan Liu, Shengzhe Yan, Zhuoyu Dai et al.|IEEE Transactions on Very Large Scale Integration (VLSI) Systems|2025Cited by 4
A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound ApplicationsJun Wang, Dashan Shang, Shengzhe Yan et al.|IEEE Transactions on Very Large Scale Integration (VLSI) Systems|2025Cited by 1
A 28nm 51.6TOPS/W 2.22Mb/mm <sup>2</sup> System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-over-Logic 1T1C eDRAMZhaori Cong, Yongpan Liu, Shengzhe Yan et al.|Unknown|2025Cited by 1