First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (<10ns), Record-Low Energy (<10fJ) of Data Transfer and Ultra-Long Data Retention (>5000s)Menggan Liu, Ming Liu, Wei Li et al.|Unknown|2024Cited by 38
A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metricsShengzhe Yan, Ming Liu, Zhaori Cong et al.|Science China Information Sciences|2025Cited by 6
A 28nm 51.6TOPS/W 2.22Mb/mm <sup>2</sup> System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-over-Logic 1T1C eDRAMZhaori Cong, Yongpan Liu, Shengzhe Yan et al.|Unknown|2025Cited by 1
A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAMZhihang Qian, M M Liu, Ying Liu et al.|IEEE Journal of Solid-State Circuits|2026Cited by 0