Novel process to pattern selectively dual dielectric capping layers using soft-mask onlyT. Schram, S. Biesemans, Y. Okuno et al.|Unknown|2008Cited by 9
Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process WindowA. Veloso, S. Biesemans, Peter Verheyen et al.|Unknown|2007Cited by 2
Achieving low V<inf>T</inf> Ni-FUSI CMOS via lanthanide incorporation in the gate stackA. Veloso, S. Biesemans, H.Y. Yu et al.|Unknown|2007Cited by 0
Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stackA. Veloso, S. Biesemans, H.Y. Yu et al.|Solid-State Electronics|2008Cited by 0