S. Kavadias

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525/spl times/525 pixels measuring 7.5 /spl mu/m/spl times/10 /spl mu/m, and is fabricated in a 0.5-/spl mu/m CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range.

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-μm CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8° rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands.

This transceiver achieves a transmit 1dB output compression point of +15dBm, and the overall receiver noise figure is 5dB. A power gain range of >45dB/65dB for transmit/receive and a PLL synthesizer frequency range of 4.9 to 5.85GHz with -79dBc/Hz phase noise at 10kHz offset have been measured. The IC is realized in 0.5/spl mu/m SiGe BICMOS technology and occupies 17mm/sup 2/.

The IEEE 802.11ad standard supports PHY rates up to 6.7Gb/s on four 2GHz-wide channels from 57 to 64GHz. A 60GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a full-featured 802.11ad chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset includes MAC, PHY, and RF with a PCIe <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> interface and is capable of maintaining a link of 4.6Gb/s (PHY rate) at 10m.