S. Sarkar

The IEEE 802.11ad standard supports PHY rates up to 6.7 Gbps on four 2 GHz-wide channels from 57 to 64 GHz. A 60 GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a 802.11ad radio chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset is capable of maintaining a link of 4.6 Gbps (PHY rate) at 10 m.

CMOS-based circuits operating at mm-wave frequencies have emerged in the past few years. This paper discusses the integration of a 60GHz CMOS single-chip transmitter and a single- chip receiver using a standard 90nm CMOS technology demonstrating a reliable solution for 60GHz single-chip radio. Proper transistor layout, complete and accurate modeling and optimized parasitic extraction method enabled the robust design of the wideband super-heterodyne architecture to support the entire 57- to-66GHz band. The analog radio front-end is controlled by a serial digital interface and has been co-designed and integrated together with a high-speed digital signal processor including analog-to-digital conversion, high speed PHY signal processing such as frequency-offset compensation, phase tracking, FIR and DFE, to support both advanced OFDM and SCBT modulation scheme. The resulting single-chip solution enables data throughputs exceeding 7Gb/s (QPSK) and 15Gb/s (16QAM) for a total DC power budget of below 200mW in TDD operation. In combination with a low-cost FR4-based packaging technology, it provides a high-performance cost-effective solution for a wide range of high volume consumer electronic applications.

In this paper, we demonstrate the development of advanced three-dimensional (3-D) low-temperature co-fired ceramic (LTCC) system-on-package (SOP) passive components for compact low-cost millimeter-wave wireless front-end modules. Numerous miniaturized easy-to-design passive circuits that can be used as critical building blocks for millimeter-wave SOP modules have hereby been realized with high-performance and high-integration potential. One miniaturized slotted-patch resonator has been designed by the optimal use of vertical coupling mechanism and transverse cuts and has been utilized to realize compact duplexers (39.8/59 GHz) and three- and five-pole bandpass filters by the novel 3-D (vertical and parallel) deployment of single-mode patch resonators. Measured results agree very well with the simulated data. One multiplexing filter, called the directional channel-separation filter, that can also be used in mixer applications shows insertion loss of <3 dB over the bandpass frequency band and a rejection /spl sim/25 dB at around 38.5 GHz over the band-rejection section. LTCC fabrication limitations have been overcome by using vertical coupling mechanisms to satisfy millimeter-wave design requirements. Lastly, a double-fed cross-shaped microstrip antenna has been designed for the purpose of doubling the data throughput by means of a dual-polarized wireless channel, covering the band between 59-64 GHz. This antenna can be easily integrated into a wireless millimeter-wave link system.

A 144-element phased array transceiver is realized using a modular tiled approach that supports 802.11ad, MCS12 single carrier 16-quadratic-amplitude modulation (QAM) 4.6 Gbps, in the 60-GHz band. It consists of a system-on-a chip (SOC) (MAC/PHY/BB to IF) in 28-nm CMOS, and one IF-to-60-GHz transceiver master chip driving twelve 60-GHz phased array transceiver slave chips fabricated in a 40-nm CMOS. Using the master-slave configuration, the 60-GHz transceiver with 12 phase-controlled TX/RX slices is expanded to 144 phase-controlled slices. Each final TX/RX slice is then connected to two patch antennas on LTCC substrate. A tiled approach is used to create the 288 patch antenna array out of six identical tiles each with two slave 60-GHz transceivers connected to a 48-element antenna array. The single tile phased array with 48 antennas has a measured beam steering scan angle of 60° in azimuth and 10° in elevation. The full phased array transceiver with 288 antennas has a measured over the air (OTA) max effective isotropic radiated power (EIRP) of 51 dBm at saturated power (PSAT), and EIRP of 44.8 dBm with -22 dB EVM for MCS12 (16QAM-4.6 Gbps) at broadside. It has an OTA measured sensitivity of -87.3 and -80.4 dBm for MCS9 (QPSK-2.5 Gbps) and MCS12, respectively, at broadside. A packet error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> was measured for MCS9 and MCS12 with an OTA input power of -85 and -77.5 dBm, respectively, for the full phased array transceiver at broadside.

Electronics packaging evolution involves system, technology, and material considerations. In this paper, we present a novel three-dimensional (3-D) integration approach for system-on-package (SOP)-based solutions for wireless communication applications. This concept is proposed for the 3-D integration of RF and millimeter (mm) wave embedded functions in front-end modules by means of stacking substrates using liquid crystal polymer (LCP) multilayer and /spl mu/BGA technologies. Characterization and modeling of high-Q RF inductors using LCP is described. A single-input-single-output (SISO) dual-band filter operating at ISM 2.4-2.5 GHz and UNII 5.15-5.85 GHz frequency bands, two dual-polarization 2/spl times/1 antenna arrays operating at 14 and 35 GHz, and a WLAN IEEE 802.11a-compliant compact module (volume of 75/spl times/35/spl times/0.2 mm/sup 3/) have been fabricated on LCP substrate, showing the great potential of the SOP approach for 3-D-integrated RF and mm wave functions and modules.