A single-chip digitally calibrated 5.15~5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN
Iason Vassiliou(Athena Group (United States)), K. Vavelidis(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), T. Georgantas(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), S. Plevridis(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), N. Haralabidis(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), G. Kamoulakos(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), C. Kapnistis(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), S. Kavadias(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), Y. Kokolakis(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), P. Merakos(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), Jacques C. Rudell, Akifumi Yamanaka(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), S. Bouras(Athena Research and Innovation Center In Information Communication & Knowledge Technologies), I. Bouras(Athena Research and Innovation Center In Information Communication & Knowledge Technologies)
The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-μm CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8° rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .