K.W. Guarini

We show a simple, robust, chemical route to the fabrication of ultrahigh-density arrays of nanopores with high aspect ratios using the equilibrium self-assembled morphology of asymmetric diblock copolymers. The dimensions and lateral density of the array are determined by segmental interactions and the copolymer molecular weight. Through direct current electrodeposition, we fabricated vertical arrays of nanowires with densities in excess of 1.9 x 10(11) wires per square centimeter. We found markedly enhanced coercivities with ferromagnetic cobalt nanowires that point toward a route to ultrahigh-density storage media. The copolymer approach described is practical, parallel, compatible with current lithographic processes, and amenable to multilayered device fabrication.

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers. This process provides the shortest distance between the stacked layers (<2 µm), the highest interconnection density (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> vias/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the /spl beta/ ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124/spl mu/m/sup 2/ half-cell) and full 8T (0.1998/spl mu/m/sup 2/) cells to date.

We are inspired by the beauty and simplicity of self-organizing materials and the promise they hold for enabling continued improvements in semiconductor technology. Self assembly is the spontaneous arrangement of individual elements into regular patterns; under suitable conditions, certain materials self organize into useful nanometer-scale patterns of importance to high-performance microelectronics applications. Polymer self assembly is a nontraditional approach to patterning integrated circuit elements at dimensions and densities inaccessible to traditional lithography methods. We review here our efforts in IBM to develop and integrate self-assembly processes as high-resolution patterning alternatives and to demonstrate targeted applications in semiconductor device fabrication. We also provide a framework for understanding key requirements for the adoption of polymer self-assembly processes into semiconductor technology, as well as a discussion of the ultimate dimensional scalability of the technique.

We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over planar structures. Our process uses a diblock copolymer thin film as a mask for dry etching to roughen a silicon surface on a 30 nm length scale, which is well below photolithographic resolution limits. Electron microscopy correlates measured capacitance values with silicon etch depth, and the data agree well with a geometric estimate. This block copolymer nanotemplating process is compatible with standard semiconductor processing techniques and is scalable to large wafer dimensions.