Stable SRAM cell design for the 32 nm node and beyond
L. Chang(IBM (United States)), David Fried(IBM (United States)), J. M. Hergenrother(IBM (United States)), J.W. Sleight, R.H. Dennard(IBM (United States)), Robert K. Montoye(IBM (United States)), L. Šekarić(IBM (United States)), Sharee J. McNab(IBM (United States)), Anna W. Topol(IBM (United States)), Charlotte Adams(IBM (United States)), K.W. Guarini(IBM (United States)), Wilfried Haensch(IBM (United States))
Cited by 566
Abstract
SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the /spl beta/ ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124/spl mu/m/sup 2/ half-cell) and full 8T (0.1998/spl mu/m/sup 2/) cells to date.
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