Cited by 419
Texas Instruments (United States)
Publishes on Electrostatic Discharge in Electronics, Semiconductor materials and devices, Integrated Circuits and Semiconductor Failure Analysis. 90 papers and 2.7k citations.
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The trends in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits. It is shown that as feature sizes are reduced, good ESD performance can be obtained provided the negative effects of the shallower junctions are offset by the positive effects of the reduction in the effective channel lengths. Hence, processes and protection circuits with feature sizes as small as 0.25 /spl mu/m can be developed without degrading ESD robustness.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.
Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per TX/RX pair