The impact of technology scaling on ESD robustness and protection circuit designA. Amerasekera, C. Duvvury|IEEE Transactions on Components Packaging and Manufacturing Technology Part A|1995 The trends in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits. It is shown that as feature sizes are reduced, good ESD performance can be obtained provided the negative effects of the shallower junctions are offset by the positive effects of the reduction in the effective channel lengths. Hence, processes and protection circuits with feature sizes as small as 0.25 /spl mu/m can be developed without degrading ESD robustness.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulationsA circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.
ESD: a pervasive reliability concern for IC technologiesC. Duvvury, A. Amerasekera|Proceedings of the IEEE|1993 Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Dynamic gate coupling of NMOS for efficient output ESD protectionA dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported. The authors discuss the gate coupling phenomenon for NMOS transistors and its effect under ESD transient conditions. A dynamic gate-coupled device was studied to understand the gate coupling effect. The authors present the complete phenomena and results for nonsilicided devices as well as for silicided structures. The measured ESD stress results are given. The gate coupling effect and device operation under ESD are explained by using modeling and simulation results. The design issues for optimum output ESD protection are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processesThe effect of salicides and the influence of the local substrate potential on ESD performance of deep submicron nMOS transistors have been studied. It is shown that salicidation causes a strong dependence of ESD performance on effective channel length in these devices. Salicides also impact the behavior of the lateral npn parasitic bipolar transistor by affecting the emitter efficiency. A higher local substrate potential has been shown to have a positive impact on ESD performance. Based on these results we have designed and demonstrated a substrate triggered nMOS protection circuit which provides >2 kV ESD performance in a fully salicided process.