Reliability-Aware Ultra-Scaled IDG-InGaZnO-FET Compact Model to Enable Cross-layer Co-design for Highly Efficient Analog Computing in 2T0C-DRAM
Lihua Xu(Jiamusi University), Ming Liu(China Academy of Space Technology), Shijie Huang(Shanghai University of Electric Power), Chunmeng Dou(Chinese Academy of Sciences), Linfang Wang(Chinese Academy of Sciences), Guanhua Yang(Guangxi University of Science and Technology), Zhidao Zhou(Chinese Academy of Sciences), Zhi Li(Fraunhofer Institute for Integrated Circuits), Ling Li(Xiamen University), Kaifei Chen(Chinese Academy of Sciences), Lingfei Wang(Fraunhofer Institute for Integrated Circuits), Yue Zhao(Emilio Aguinaldo College), Jingrui Guo(Chinese Academy of Sciences)
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