CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing
Ramanathan Gandhi(Agency for Science, Technology and Research), Sungjoo Lee(Tohoku University), Navab Singh(Agency for Science, Technology and Research), Kaustav Banerjee(University of California, Santa Barbara), Zhixian Chen(ShanghaiTech University)
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