High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

Abstract

A 32 nm logic technology for high performance microprocessors is described. 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32 nm or 28 nm logic technology. NMOS drive currents are 1.62 mA/um Idsat and 0.231 mA/um Idlin at 1.0 V and 100 nA/um I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> . PMOS drive currents are 1.37 mA/um Idsat and 0.240 mA/um Idlin at 1.0 V and 100 nA/um I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> . The impact of SRAM cell and array size on Vccmin is reported.