CNTFET-Based Design of Ternary Logic Gates and Arithmetic CircuitsSheng Lin, Fabrizio Lombardi, Yong-Bin Kim|IEEE Transactions on Nanotechnology|2009Cited by 599
A novel CNTFET-based ternary logic gate designSheng Lin, Fabrizio Lombardi, Yong-Bin Kim|Unknown|2009Cited by 150
Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node UpsetSheng Lin, Fabrizio Lombardi, Yong-Bin Kim|IEEE Transactions on Device and Materials Reliability|2011Cited by 113
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stabilitySheng Lin, Fabrizio Lombardi, Yong-Bin Kim|Integration|2010Cited by 79
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft ErrorsSheng Lin, Fabrizio Lombardi, Yong-Bin Kim|IEEE Transactions on Very Large Scale Integration (VLSI) Systems|2010Cited by 68