Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset
Sheng Lin(Qingdao Agricultural University), Fabrizio Lombardi(Northeastern University), Yong-Bin Kim(Northeastern University)
Cited by 113
Related Papers
CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
|IEEE Transactions on Nanotechnology|2009|599
A Hierarchical Framework of Cloud Resource Allocation and Power Management Using Deep Reinforcement Learning
|Unknown|2017|285
A Survey of Stochastic Computing Neural Networks for Machine Learning Applications
|IEEE Transactions on Neural Networks and Learning Systems|2020|197
Design of a Ternary Memory Cell Using CNTFETs
|IEEE Transactions on Nanotechnology|2012|157
A novel CNTFET-based ternary logic gate design
|Unknown|2009|150