Buried Power Rails and Back-side Power Grids: Arm<sup>®</sup> CPU Power Delivery Network Design Beyond 5nmDivya Prasad, Saurabh Sinha, Rogier Baert et al.|Unknown|2019Cited by 69
A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology NodesS. S. Teja Nibhanupudi, Jaydeep P. Kulkarni, Odysseas Zografos et al.|IEEE Transactions on Electron Devices|2022Cited by 20
Buried Power Rails and Back-side Power Grids: Arm (R) CPU Power Delivery Network Design Beyond 5nmP. Divya, Anshul Gupta, S. S. Teja Nibhanupudi et al.|IEEE Conference Proceedings|2019Cited by 0