S. Khawam

This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.

This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself with respect to routing, switching and data packet size with the changing communication requirements of the system at run time, thus aiming to provide low latency, low power and high data throughput. Simulation results and a prototype implementation of the idea have shown its efficiency when simulated under different traffic condition at a negligible area overhead

the IEEE 802.11e standard has been introduced recently for providing quality of service (QoS) capabilities in the emerging wireless local area networks. This standard introduces a contention window based enhanced distributed channel access (EDCA) technique that provides a prioritized traffic to guarantee the minimum bandwidth needed for time critical applications. However, the EDCA technique resets statically the contention window of the mobile station after each successful transmission. This static behavior does not adapt to the network state hence reduces the network usage and results in bad performance and poor link utilization whenever the demand for link utilization increases. This paper proposes a new adaptive differentiation technique for IEEE 802.11e wireless local area networks that takes into account the network state before resetting the contention window. The performance of the proposed technique is evaluated compared to the original differentiation techniques of the IEEE 802.11a and IEEE 802.11e standards. Preliminary results show that the proposed adaptive technique enhances the channel utilization and increases throughput.

This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distributed high performance instruction cell based reconfigurable systems. Unlike other typical scheduling methods, it considers the placement and routing effect, register assignment and advanced operation chaining compilation technique to generate higher performance scheduled code. The effectiveness of this approach is demonstrated here using a recently developed industrial distributed reconfigurable instruction cell based architecture [ 11]. The results show that schedules using this approach achieve equivalent throughput to VLIW architectures but at much lower power consumption.

Summary form only given. Domain-specific reconfigurable arrays are embedded arrays optimized for one domain of applications providing performance improvements over generic embedded field programmable gate arrays (FPGAs). An embedded reconfigurable array that targets distributed arithmetic (DA) implementations is presented. DA includes calculations that are commonly found in multimedia applications, such as filtering and discrete cosine transform (DCT). Two benchmark DCT circuits are implemented on the array, on conventional FPGAs and on hardwired cores. The performance measured shows considerable improvements in area, power consumption and timing when comparing the presented array with FPGAs. Experimental results are provided which demonstrate the suitability of our architecture in low-power system-on-chip platforms targeting portable mobile devices.