Ahmet T. Erdogan

The Microarray is a technique used by biologists to perform many genome experiments simultaneously, which produces very large datasets. Analysis of these datasets is a challenge for scientists especially as the number of genome databases is increasing rapidly every year. K-means clustering is an unsupervised data mining technique used widely by bioinformaticians to analyze Microarray data. However, K-means can take between a few seconds to several days to process Microarray data depending on the size of these datasets. This puts a limit on the complexity of biological problems which can be asked by bioinfomaticians, and hence may result in an incomplete solution to the problem. In order to overcome such problems, we propose a highly parallel hardware design to accelerate the K-means clustering of Microarray data by implementing the K-means algorithm in Field Programmable Gate Arrays (FPGA). Our implementation is particularly suitable for server solution as it allows for processing many different datasets simultaneously. We have designed, and implemented five k-mean cores on Xilinx Virtex4 XC4VLX25 FPGA, and tested them on a sample of real Yeast Microarray data. Our design achieved about 51.7× speed-up when compared to a software model while being 206.8× more energy efficient.

A 512 × 16 single photon avalanche diode (SPAD)based line sensor is designed in a 0.13-μm CMOS image sensor technology for time-resolved multispectral beam scanned imaging. The sensor has 23.78-μm pixel pitch and incorporates one SPAD array with 49.31% fill factor optimized for detection in the blue-green spectral region, and a second array at 15.75% fill factor optimized for the red-near-infrared response spectral region. Each pixel contains a 32-bin histogramming time-to-digital converter (TDC) with a mean time resolution of 51.20 ps. Histogram bin resolutions are adjustable from 51.20 ps to 6.55 ns per bin. The line sensor can operate in single photon counting (SPC) mode (102.1 giga-events/s), timecorrelated SPC (TCSPC) mode (192.4 million-events/s) or on-chip histogramming mode (16.5 giga-events/s), increasing the count rate up to 85 times compared to TCSPC mode. Sensor capability is demonstrated through spectral fluorescence lifetime imaging, resolving three fluorophore populations with distinct fluorophore lifetimes.

We present a digital architecture for fast acquisition of time correlated single photon counting (TCSPC) events from a 32×32 complementary metal oxide semiconductor (CMOS) single photon avalanche detector (SPAD) array (Megaframe) to the computer memory. Custom firmware was written to transmit event codes from 1024-TCSPC-enabled pixels for fast transfer of TCSPC events. Our 1024-channel TCSPC system is capable of acquiring up to 0.5×10(9) TCSPC events per second with 16 histogram bins spanning a 14 ns width. Other options include 320×10(6) TCSPC events per second with 256 histogram bins spanning either a 14 or 56 ns time window. We present a wide-field fluorescence microscopy setup demonstrating fast fluorescence lifetime data acquisition. To the best of our knowledge, this is the fastest direct TCSPC transfer from a single photon counting device to the computer to date.

This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself with respect to routing, switching and data packet size with the changing communication requirements of the system at run time, thus aiming to provide low latency, low power and high data throughput. Simulation results and a prototype implementation of the idea have shown its efficiency when simulated under different traffic condition at a negligible area overhead