Design of linear ramp generator for ADCS R Ashwini, S. P. Joy Vasantha Rani, M. Sivakumar|Unknown|2017Cited by 9
An area efficient, high-frequency digital built-in self-test for analogue to digital converterM. Sivakumar, S. P. Joy Vasantha Rani|International Journal of Electronics|2018Cited by 6
Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error EstimationM. Sivakumar, S. P. Joy Vasantha Rani|Journal of Circuits Systems and Computers|2018Cited by 2
Design of digital built-in self-test for analog to digital converterM. Sivakumar, S. P. Joy Vasantha Rani|Unknown|2016Cited by 1
Time domain modelled ADC BIST with ramp noise projectionM. Sivakumar, S. P. Joy Vasantha Rani|International Journal of Electronics|2019Cited by 1