A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery
Mike Harwood(Texas Instruments (United Kingdom)), N. Warke(Texas Instruments (United States)), R. S. Simpson(Texas Instruments (United Kingdom)), Tom Leslie(Texas Instruments (United Kingdom)), A. Amerasekera(Texas Instruments (United States)), Sean Batty(Texas Instruments (United Kingdom)), D. Colman(Texas Instruments (United Kingdom)), Eugenia Carr(Texas Instruments (United Kingdom)), Venu Gopinathan(Texas Instruments (India)), Steve Hubbins(Texas Instruments (United States)), P.C. Hunt(Texas Instruments (United Kingdom)), Andy Joy(Texas Instruments (United Kingdom)), Pulkit Khandelwal(Texas Instruments (United Kingdom)), Bob Killips(Texas Instruments (United Kingdom)), Thomas Krause(Texas Instruments (United States)), Shaun Lytollis(Texas Instruments (United Kingdom)), A. J. Pickering(Texas Instruments (United Kingdom)), Mark Saxton(Texas Instruments (United States)), David Sebastio(Texas Instruments (United Kingdom)), Graeme Swanson(Texas Instruments (United Kingdom)), Andre Szczepanek(Texas Instruments (United Kingdom)), Terry Ward(Texas Instruments (United Kingdom)), Jeff Williams(Texas Instruments (United Kingdom)), Richard Williams(Texas Instruments (United Kingdom)), Tom Willwerth(Texas Instruments (United States))
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Abstract
A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per TX/RX pair
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