Xun Ding

Silicon single-photon avalanche detectors are becoming increasingly significant in research and in practical applications due to their high signal-to-noise ratio, complementary metal oxide semiconductor compatibility, room temperature operation, and cost-effectiveness. However, there is a trade-off in current silicon single-photon avalanche detectors, especially in the near infrared regime. Thick-junction devices have decent photon detection efficiency but poor timing jitter, while thin-junction devices have good timing jitter but poor efficiency. Here, we demonstrate a light-trapping, thin-junction Si single-photon avalanche diode that breaks this trade-off, by diffracting the incident photons into the horizontal waveguide mode, thus significantly increasing the absorption length. The photon detection efficiency has a 2.5-fold improvement in the near infrared regime, while the timing jitter remains 25 ps. The result provides a practical and complementary metal oxide semiconductor compatible method to improve the performance of single-photon avalanche detectors, image sensor arrays, and silicon photomultipliers over a broad spectral range.The performance of silicon single-photon avalanche detectors is currently limited by the trade-off between photon detection efficiency and timing jitter. Here, the authors demonstrate how a CMOS-compatible, nanostructured, thin junction structure can make use of tailored light trapping to break this trade-off.

In the relentless pursuit of quantum computational advantage, we present a significant advancement with the development of Zuchongzhi 3.0. This superconducting quantum computer prototype, comprising 105 qubits, achieves high operational fidelities, with single-qubit gates, two-qubit gates, and readout fidelity at 99.90%, 99.62%, and 99.13%, respectively. Our experiments with an 83-qubit, 32-cycle random circuit sampling on the Zuchongzhi 3.0 highlight its superior performance, achieving 1×10^{6} samples in just a few hundred seconds. This task is estimated to be infeasible on the most powerful classical supercomputers, Frontier, which would require approximately 5.9×10^{9} yr to replicate the task. This leap in processing power places the classical simulation cost 6 orders of magnitude beyond Google's SYC-67 and SYC-70 experiments [Morvan et al., Nature 634, 328 (2024)10.1038/s41586-024-07998-6], firmly establishing a new benchmark in quantum computational advantage. Our work not only advances the frontiers of quantum computing but also lays the groundwork for a new era where quantum processors play an essential role in tackling sophisticated real-world challenges.

Quantum error correction (QEC) enables practical quantum computing by encoding logical qubits in many physical qubits, which can exponentially suppress the logical error rate with increasing code size provided that the physical error rate is below a critical threshold. However, the leakage of quantum information from the computational subspace presents a critical challenge to the development of scalable QEC, which creates long-lived, correlated errors that spread across space and time. Here, we demonstrate a quantum memory operating below the threshold by implementing an all-microwave leakage suppression architecture on a distance-7 surface code. We achieve a logical error suppression factor of Λ=1.40(6), definitively reversing the above-threshold scaling (Λ<1) caused by unmitigated leakage. This scheme integrates a hardware-efficient leakage reduction unit for data qubits with a fast, unconditional reset for ancilla qubits, suppressing the average leakage population after 40 cycles by a factor of 72 to 6.4(5)×10^{-4}. Our results demonstrate the viability of all-microwave control architectures for suppressing critical errors at scale, paving the way for more advanced quantum error correction implementations.

We present a surface textured Si SPAD with improved detection efficiency and without sacrificing dark count rate or jitter distribution. Texturing reduces reflection, allows weak light trapping and is CMOS and lithography compatible.