Maliang Liu

In the relentless pursuit of quantum computational advantage, we present a significant advancement with the development of Zuchongzhi 3.0. This superconducting quantum computer prototype, comprising 105 qubits, achieves high operational fidelities, with single-qubit gates, two-qubit gates, and readout fidelity at 99.90%, 99.62%, and 99.13%, respectively. Our experiments with an 83-qubit, 32-cycle random circuit sampling on the Zuchongzhi 3.0 highlight its superior performance, achieving 1×10^{6} samples in just a few hundred seconds. This task is estimated to be infeasible on the most powerful classical supercomputers, Frontier, which would require approximately 5.9×10^{9} yr to replicate the task. This leap in processing power places the classical simulation cost 6 orders of magnitude beyond Google's SYC-67 and SYC-70 experiments [Morvan et al., Nature 634, 328 (2024)10.1038/s41586-024-07998-6], firmly establishing a new benchmark in quantum computational advantage. Our work not only advances the frontiers of quantum computing but also lays the groundwork for a new era where quantum processors play an essential role in tackling sophisticated real-world challenges.

This paper addresses the issue of deceptive jamming against synthetic aperture radar (SAR) by using 1-bit sampling and time-varying threshold (TVT). With 1-bit intercepted SAR signal, the multipliers involved in a convolution is replaced by xnor gates, which considerably simplify the jamming signal generation. Moreover, the TVT is used for 1-bit quantization before retransmission to retain the relative amplitude information of the jamming signal. As a result, the proposed deceptive jamming schemes are superior to their conventional counterpart in terms of realization. Effects of harmonics and oversampling are analyzed to evaluate the performance degradations caused by the 1-bit sampling and TVT. Simulation results are provided to confirm the validity of the proposed schemes.

An asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for sensor applications is presented. High linear and power efficient switching scheme is proposed. The proposed low leakage latched dynamic cell in SAR logic and wide range configurable delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 0.18 μm CMOS process covers 6-10 bit resolution and 0.5 V-0.9 V power supply range. At 10 bit mode and 0.5 V operation, the proposed SAR ADC achieves 56.36 dB SNDR and 67.96 dB SFDR with sampling rate up to 2 MS/s, corresponding to a figure-of-merit of 20.6 fJ/conversion-step. The proposed ADC core occupies an active area of about 300×700 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , and 4.68 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz respectively. The proposed AFE circuit, which is fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

This paper presents a linear-mode light detection and ranging (LiDAR) analog front-end architecture with multiplex analog-to-digital converter/time-to-digital converter (ADC/TDC). An added voltage-to-time converter (VTC) and a reused TDC are simultaneously used to implement the ADC and TDC function, thus replacing discrete ADC and TDC, saving hardware cost and reducing power consumption. A three-stage inverter-based transimpedance amplifier (TIA) with ultra-low-power, low-noise and high/low gain mode (long/short range mode) is proposed to reduce its influence to optical signal-to-noise ratios (OSNR). The prototype TIA and ADC/TDC is fabricated in the 65-nm CMOS technology and integrated into the single-line APD-based LiDAR system. The receiver front-end of TIA and ADC/TDC only consumes 12.44-mW. The minimum detection current of the receiver front-end is less than 238 nA with bandwidth of 150MHz for long-range and weak-light detection. LiDAR achieves a measurement range of 60 m with a 70-klx direct sunlight and only 6.16 mW average laser power. Experimental results show that this architecture is suitable for low-cost multi-line integrated LiDAR applications compared to conventional architecture using ADC, TDC, ADC+TDC architecture.