Sandeep Goel

A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (TAM), the core test wrapper forms the test access infrastructure to embedded reusable cores. Various company-internal as well as industry-wide standardized but scalable wrappers have been proposed. This paper deals with the design of such core test wrappers. It gives a general architecture for wrappers, and describes how a wrapper can be built up from a library of wrapper cells which are selected on basis of the terminal types of the core. We show that the ordering and partitioning of wrapper cells and core-internal scan chains over TAM chains determine the test time of the core. An heuristic approach for the NP-hard problem of partitioning the TAM chain items for minimal test time is presented and its usage is illustrated by means of an example. Finally we sketch how wrapper generation and verification can be automated.

This paper deals with the design of test architectures for modular SOC testing. These architectures consist of wrappers and TAMs (test access mechanisms). For a given SOC, with specified parameters of modules and their tests, we design architectures which minimize the required ATE vector memory depth and test application time. In this paper, we formulate the problems of test architecture design both for modules with fixed- and flexible-length scan chains. Subsequently, we derive a formulation of an architecture-independent test time lower bound for SOCs and list the lower bound values for the 'ITC'02 SOC test benchmarks'. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and testrail architectures with serial and parallel test schedules. Experimental results for the 'ITC'02 SOC test benchmarks' show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.

The study attempts to empirically investigate the impact of ESG score on the financial variables that may affect the performance of firms in the Indian context; SEBI’s recent mandate on ESG reporting by the listed entities being the point of departure for the present discourse. A representative sample of 48 Indian firms having ESG scores under BSE-100 index is used in the analysis. The study period comprises the years 2011–2019. Static and dynamic panel regression analyses are conducted. The financial performance variables incorporated in this paper include ROA, ROE, firm size, market capitalization, PBDIT, Tobin’s Q and share price. It is demonstrated that ESG score influences these variables, however with time lags. The distinctive contribution of the current endeavour lies in establishing a long-term positive association between ESG disclosure and annual average share price for the listed firms in a developing economy like India. The results are implicative of the fact that ESG score is an emerging indicator for conceiving future financial performance and risk mitigation strategies, and therefore, of considerable importance from policy perspective.

This article deals with the design of on-chip architectures for testing large system chips (SOCs) for manufacturing defects in a modular fashion. These architectures consist of wrappers and test access mechanisms (TAMs). For an SOC with specified parameters of modules and their tests, we design an architecture that minimizes the required tester vector memory depth and test application time. In this article, we formulate the test architecture design problems for both modules with fixed- and flexible-length scan chains, assuming the relevant module parameters and a maximal SOC TAM width are given. Subsequently, we derive a formulation for an architecture-independent lower bound for the SOC test time. We analyze three types of TAM under-utilization that make the theoretical lower bound unachievable in most practical architecture instances. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and TestRail architectures with either serial or parallel test schedules. Experimental results for the ITC'02 SOC Test Benchmarks show that, compared to manual best-effort engineering approaches, we can save up to 75% in test times, while compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.

The present paper explores the association between earnings management and specific board characteristics and the firm's profitability in the Indian context. In India, the corporate ownership model is the promoter dominated shareholders model. This is the first study based on a panel data framework that employs a fixed effect model to control for time‐invariant endogeneity. It also contributes to the literature by exploring the role of the firm's profitability in transmitting the impact of audit committee independence on earnings management. The study finds that profitability is an important variable, as it moderates the association between audit committee independence and earnings management. Managers of a profit‐making company would have little need to modify their earnings. This signifies that independent audit committees are more effective monitors of earnings management in profitable firms than in non‐profitable firms. Independent directors with multiple directorships are also found to be ineffective monitors. The findings are of material significance to policymakers in analysing board effectiveness and earnings management and improving policymaking for corporate governance by using profitability and related variables.