Double image encryption method using the Arnold transform in the fractional Hartley domainJuan M. Vilardy, César O. Torres, Carlos J. Jiménez|Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE|2013 A new method for double image encryption based on the fractional Hartley transform (FrHT) and the Arnold transform (AT) is proposed in this work. The encryption method encodes the first input image in amplitude and the second input image is encoded in phase, in order to define a complex image. This complex image is successively four times transformed using FrHT and AT, and the resulting complex image represents the encrypted image. The decryption method is the same method as the encryption method applied in the inverse sense. The AT is a process of image shearing and stitching in which pixels of the image are rearranged. This AT is used in the encryption method with the purpose of spreading the information content of the two input images onto the encrypted image and to increase the security of the encrypted image. The fractional orders of the FrHTs and the parameters of the ATs correspond to the keys of the encryption-decryption method. Only when all of those keys are correct in the decryption method, the two original images can be recovered. We present digital results that confirm our approach.
Digital Images Phase Encryption Using Fractional Fourier TransformIn the present paper the fractional Fourier transform was used to make phase encryption of color digital images. The image to encrypt is placed as the phase of a complex exponential, then is fractionally transformed three times and multiplied in intermediate steps by two statistically independent random phase masks thus to obtain the encrypted image, to decrypt the coding image the encryption procedure is applied in the inverse sense to the conjugated complex of the encrypted image, then is taken the negative of the phase of the resulting function from the decryption process and the original image is obtained this way that had been encrypted. The use of the fractional Fourier transform and the phase encryption of the image add much more complexity to the decryption of the image to who wants decrypt it without being authorized. In the cryptographic algorithm implemented five keys are used, made up of three fractional orders and two random phase masks, all these keys are necessary for proper decryption affording reliability to image transference via transmission networks
Compact Spiking Neural Network Implementation in FPGASelene Maya, Rocio Reynoso, César O. Torres et al.|Lecture notes in computer science|2000 Fractional Hartley transform applied to optical image encryptionCarlos J. Jiménez, César O. Torres, L Mattos|Journal of Physics Conference Series|2011 A new method for image encryption is introduced on the basis of two-dimensional (2-D) generalization of 1-D fractional Hartley transform that has been redefined recently in search of its inverse transform We encrypt the image by two fractional orders and random phase codes. It has an advantage over Hartley transform, for its fractional orders can also be used as addictional keys, and that, of course, strengthens image security. Only when all of these keys are correct, can the image be well decrypted. Computer simulations are also perfomed to confirm the possibilty of proposed method.
On the implementation of an efficient FPGA-based CFAR processor for target detectionReal-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three version of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The proposed architecture has been implemented on a Field Programmable Gate Array (FPGA) device providing good performance improvements over software implementations. FPGA implementation results are presented and discussed.