Scott Temple

The melting curve of lithium between ambient pressure and 64 GPa is measured by detection of an abrupt change in its electrical resistivity at melting and by visual observation. Here we have used a quasi-four-point resistance measurement in a diamond anvil cell and measured the resistance of lithium as it goes through melting. The resistivity near melting exhibits a well documented sharp increase which allowed us to pinpoint the melting transition from ambient pressure to 64 GPa. Our data show that lithium melts clearly above 300 K in all pressure regions and its melting behavior adheres to the classical model. Moreover, we observed an abrupt increase in the slope of the melting curve around 10 GPa. The onset of this increase fits well to the linear extrapolation of the lower temperature bcc-fcc phase boundary.

The increasing complexity of modern Integrated Circuits (ICs) leads to systems composed of various different Intellectual Property (IPs) blocks, known as System-on-Chip (SoC). Such complexity requires strong expertise from engineers, that rely on expansive commercial EDA tools. To overcome such a limitation, an automated open-source logic synthesis flow is required. In this context, this work proposes LSOracle: a novel automated mixed logic synthesis framework. LSOracle is the first to exploit state-of-the-art And-Inverter Graph (AIG) and Majority-Inverter Graph (MIG) logic optimizers and relies on a Deep Neural Network (DNN) to automatically decide which optimizer should handle different portions of the circuit. To do so, LSOracle applies k-way partitioning to split a DAG into multiple partitions and uses a to chose the best-fit optimizer. Post-tech mapping ASIC results, targeting the 7nm ASAP standard cell library, for a set of mixed-logic circuits, show an average improvement in area-delay product of 6.87% (up to 10.26%) and 2.70% (up to 6.27%) when compared to AIG and MIG, respectively. In addition, we show that for the considered circuits, LSOracle achieves an area close to AIGs (which delivered smaller circuits) with a similar performance of MIGs, which delivered faster circuits.

Significance The emergence of exotic quantum states, such as fluid ground state and two-component superconductivity and superfluidity, in a compressed light metallic system has been entertained theoretically for metallic phases of hydrogen. The difficulty of compressing hydrogen to metallization densities has prevented experimental proof of these effects. Studying lithium, which is isovalent to hydrogen and the lightest metal, is considered as a route to studying the lattice quantum effects in a dense light metallic system. Here, by comparing the superconductivity of lithium isotopes under pressure, we present evidence that properties of lithium at low temperature may significantly be dominated by its lattice quantum dynamics. This study is the first experimental report on superconducting properties of 6 Li, the lightest superconducting material.

Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabrication. However, when deciding which parts of a design to redact, there are a number of practical issues that designers need to consider, including area and timing overheads, as well as security factors. Adapting an open-source FPGA fabric generation flow, we perform a case study to explore the trade-offs when redacting different modules of open-source intellectual property blocks (IPs) and explore how different parts of an eFPGA contribute to the security. We provide new insights into the feasibility and challenges of using eFPGA-based redaction as a security solution.

In harsh environments such as space, radiation and charged particles cause Single-Event Effects, faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy, are very effective against Single-Event Transients (SETs), but incur a minimum of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> cost in area. Single-Event Upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process, going through every memory word looking for errors to repair. It involves a non-negligible Time To Detect (TTD) before repair, during which other events can occur and compromise the system. Field Programmable Gate Arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design integrity in harsh conditions. In this paper, we propose In-Memory Error Code Correction Checking (IMECCC), a method to replace memory scrubbing and improve FPGA configuration memory protection in high radiation environments. Our method allows asynchronous SEU detection, and replaces the scrubbing’s variable time to detect with a fixed TTD. We show that IMECCC reduces FPGA’s TTD by at least 116, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$000\times $ </tex-math></inline-formula> on average, with an area increase of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.56\times $ </tex-math></inline-formula> , using a test architecture resembling a Xilinx Virtex 5 QV at a 60MHz scrubbing frequency.