Uygar E. Avci

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 13 nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> . Also, P-TFET current-drive is between 1× to 0.5× of N-TFET, depending on choice of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> . There are many challenges to realizing TFETs in products, such as the requirement of high quality III-V materials and oxides with very thin body dimensions, and the TFET's layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

Ferroelectric hafnium and zirconium oxides have undergone rapid scientific development over the last decade, pushing them to the forefront of ultralow-power electronic systems. Maximizing the potential application in memory devices or supercapacitors of these materials requires a combined effort by the scientific community to address technical limitations, which still hinder their application. Besides their favorable intrinsic material properties, HfO2–ZrO2 materials face challenges regarding their endurance, retention, wake-up effect, and high switching voltages. In this Roadmap, we intend to combine the expertise of chemistry, physics, material, and device engineers from leading experts in the ferroelectrics research community to set the direction of travel for these binary ferroelectric oxides. Here, we present a comprehensive overview of the current state of the art and offer readers an informed perspective of where this field is heading, what challenges need to be addressed, and possible applications and prospects for further development.

The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the recent progress in the fabrication of complementary metal-oxide-semiconductor (CMOS) devices based on stacked 2D TMD nanoribbons and specifically highlight issues that still need to be resolved by the 2D community in five crucial research areas: contacts, channel growth, gate oxide, variability, and doping. While 2D TMD transistors have great potential, more research is needed to understand the physical interactions of 2D materials at the atomic scale. 2D semiconductors have been proposed as a potential option to replace or complement silicon electronics at the nanoscale. Here, the authors discuss the recent progress and remaining challenges that need to be addressed by the academic and industrial research communities towards the commercialization of 2D transistors.

2D CMOS transistors fabricated with transition metal dichalcogenide (TMD) materials are a potential replacement for silicon transistors at sub-12 nm channel length [L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> ]. We demonstrate record NMOS contacts using a high melting point metal, down to 146 Ω-µm contact resistance (Rc). We present the best PMOS performance on a grown monolayer WSe2 film with 50 µA/µm Ion and 141 mV/dec sub-threshold swing (SS) using a Ru contact metal, showing record PMOS contact resistance, Rc = 2.7 kΩ-µm. For the first time, we present 300 mm wafer growth options of 4 different 2D TMD films: MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , WS2, WSe2, MoSe2 that were grown at BEOL compatible temperatures. On unpassivated channel devices we show two methods of channel curing. First, N2 desiccation can improve ION (~2x) and SS (~0.6×) simultaneously. Secondly, FGA annealing can improve bare channel devices by increasing their median Ion by 10× and lowering their SS by almost 50%. Finally, we benchmark our results against leading grown TMD devices, demonstrating record drive-currents among devices with good SS.