Carrier Mobility in a 55-nm CMOS at 4 K: Characterization, Modeling, and Circuit Implications

Abstract

Accurate characterization of carrier mobility in scaled CMOS at cryogenic temperatures is essential for applications such as quantum computing. This article presents a comprehensive study of effective carrier mobility in a 55-nm bulk CMOS technology at 4 K. Using a physics-based extraction technique, we decompose the inverse mobility into its constituent weak-field (Coulomb) and strong-field (surface roughness) scattering components. The characterization across various device geometries and threshold voltage options reveals that mobility degradation at 4 K is primarily governed by the weak-field component. A significant finding is the asymmetric width dependence, where PMOS mobility is strongly enhanced in narrow channels due to mechanical stress, while NMOS mobility remains largely unaffected. An empirical model for the key scattering parameters is developed and validated against a verification set of experimental data, demonstrating excellent predictive accuracy for drain current. The results provide critical physical insights and a direct pathway for developing accurate cryogenic compact models, with important circuit implications for device selection and layout optimization.