A 300-GHz-Band 36-Gb/s Scalable 2-D Phased-Array CMOS Double Superheterodyne Receiver
Satoshi Tanaka(Hiroshima University), Minoru Fujishima(Hiroshima University), Shuhei Amakawa(Hiroshima University), Shunichi Kubo, Akifumi Kasamatsu(National Institute of Information and Communications Technology), Kunio Sakakibara(Nagoya Institute of Technology), Takeshi Yoshida(Hiroshima University), Kyoya Takano(Hiroshima University), Shinsuke Hara(National Institute on Consumer Education), Yoshiki Sugimoto(Nagoya Institute of Technology)
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