Parasitic Parameter Extraction for Calibration Standards Using an Optimization Strategy

Abstract

This article presents a novel extraction method for parasitic parameters of on-wafer calibration standards using an optimization strategy. Based on the physical models of the calibration standards, the parasitic parameters of all calibration standards can be extracted using the Bayesian optimization method with a fast calculation speed and high accuracy. Compared with the conventional thru-reflect-line (TRL) extraction method, the proposed approach can work well in systems with high crosstalk. The methodology is validated through on-wafer measurements using a ground–signal–ground (GSG) probe with low crosstalk and a ground–signal (GS) probe with high crosstalk. The proposed method shows a comparable accuracy with the TRL method in the low-crosstalk case, while it has higher accuracy in the high-crosstalk scenario.