1V high-speed digital circuit technology with 0.5μm multi-threshold CMOS

Abstract

A 1-V high-speed and low-power digital circuit technology with 0.5/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed. This technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI. Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less. High-threshold voltage MOSFETs suppress the stand-by leakage circuit during the sleep period. The technology has achieved logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation. To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle. An 18-MHz operation at 1 V was obtained using a 0.5-/spl mu/m MT-CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>