An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC

Abstract

A new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC is presented. By splitting the MSB capacitor into b - 1 binary scaled sub-capacitors, the average switching energy of the array can be reduced by 37% compared to a conventional switching method. A formal solution of the switching energy in four different switching methods is included, and the equations are verified using HSPICE simulations of a 10b capacitor array in a 0.18 /spl mu/m CMOS process.