Improving the ESD failure threshold of silicided n-MOS output transistors by ensuring uniform current flow

Abstract

The authors describe and extend the present understanding of the high-current behavior of the simple single-poly finger n-MOS transistor. They present a model for the failure of the ladder structure n-MOS output device based on both the structure of the device and the behavior of its constituent n-MOS transistors. This model is able to show why the failure threshold of the output n-MOS device behaves as it does. Solutions that have been shown to improve the electrostatic discharge (ESD) failure threshold are described. The test environment and the process technology used for fabrication are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>