A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu(National Cheng Kung University), Soon-Jyh Chang(National Cheng Kung University), Guan‐Ying Huang(National Cheng Kung University), Ying-Zu Lin(National Cheng Kung University), Chung-Ming Huang(Himax (Taiwan)), Chih‐Hao Huang(Himax (Taiwan)), Linkai Bu(Himax (Taiwan)), Chih-Chung Tsai(Himax (Taiwan))
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Abstract
This paper presents a 10 b SAR ADC with a binary-scaled error compensation technique. The prototype occupies an active area of 155 × 165 ¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 65 nm CMOS. At 100 MS/S, the ADC achieves an SNDR of 59.0 dB and an SFDR of 75.6 dB, while consuming 1.13 mW from a 1.2 V supply. The FoM is 15.5 fJ/conversion-step.
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