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Michael Adler(Intel (United States)), Kermin Fleming(Massachusetts Institute of Technology), Angshuman Parashar(Intel (United States)), Michael Pellauer(Massachusetts Institute of Technology), Joel Emer(Intel (United States))
Unknown
February 27, 2011
Cited by 89

Abstract

Developers accelerating applications on FPGAs or other reconfigurable logic have nothing but raw memory devices in their standard toolkits. Each project typically includes tedious development of single-use memory management. Software developers expect a programming environment to include automatic memory management. Virtual memory provides the illusion of very large arrays and processor caches reduce access latency without explicit programmer instructions.


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