Design of a pixel cell optimized for a data push architecture readout

Abstract

A pixel cell has been designed which has been optimized for a data push architecture readout. It retains the features of preceding designs which allow time stamping, analog signal processing, XY address recording, ghost elimination and sparse data transmission. It eliminates a number of problems inherent in previous designs by use of sampled data techniques, destructive readout sampled data techniques, and current mode output drivers. This document examines the motivation for this new pixel and covers the theory of operation of the various blocks. A discussion of the tradeoffs affecting speed, power, device size, and radiation stability is included as well.