Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

Upasana(University of Delhi), Mridula Gupta(University of Delhi), Rakhi Narang(University of Delhi), Manoj Saxena(University of Delhi)
IEEE Transactions on Electron Devices
August 14, 2015
Cited by 57


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