An experimental 220 MHz 1 Gb DRAM
Masashi Horiguchi(Hitachi (United States)), T. Sakata(Hitachi (United States)), Tomonori Sekiguchi(Hitachi (Japan)), S. Ueda(Hitachi (Japan)), Hitoshi Tanaka(Hitachi (Japan)), E. Yamasaki(Hitachi (Japan)), Y. Nakagome(Hitachi (Japan)), Masakazu Aoki(Hitachi (Japan)), I. Kaga, M. Ohkura, R. Nagai, Fabrício Murai, T. Tanaka, S. Iijima, N. Yokoyama, Y. Gotoh, K. Shoji, T. Kisu, Hiroyuki Yamashita, Takashi Nishida, Eiji Takeda
Cited by 29
Abstract
With the arrival of the multimedia era, high-data-rate memory LSIs are becoming increasingly important to keep up with high-speed CPUs, graphics processors, and other consumers of stored data. Video editing and replaying of high-definition television in particular require a high bandwidth. This paper presents two circuit technologies for a synchronously operating high-data-rate 1 Gb DRAM: a distributed-column-control architecture reducing the burst-mode cycle time, and a ringing-canceling output buffer ensuring reliable high-speed data transfer.
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