Achieving 10Gbps Line-rate Key-value Stores with FPGAs

Abstract

Distributed in-memory key-value stores such as mem-cached have become a critical middleware application within current web infrastructure. However, typical x86-based systems yield limited performance scalability and high power consumption as their architecture with its optimization for single thread performance is not well-matched towards the memory-intensive and parallel na-ture of this application. In this paper we present the design of a novel memcached architecture implemented on Field Programmable Gate Arrays (FPGAs) which is the first in literature to achieve 10Gbps line rate process-ing for all packet sizes. By transformation of the func-tionality into a dataflow architecture, the implementation can not only provide significant speed-up but also oper-ate at a lower power consumption than any x86. More specifically, with our prototype we have measured an in-crease of up to a factor of 36x in requests per second per Watt that can be serviced in comparison to the best published numbers for regular servers with optimized software. Additionally, we show that through the tight integration of network interface, memory and compute, round trip latency can be reduced down to below 4.5 mi-croseconds. 1